1. Field of the Invention
The present invention relates to a matched filter and a method of synchronizing the operation timing of a receiver with a phase of a wave signal transmitted from a sender in a code division multiple access (referred to simply as "CDMA") system adaptable for a spread spectrum communication (abbreviated to "SSC") system.
2. Description of the Related Art
There have so far been proposed a wide variety of matched filters for synchronizing the operation timing of the receiver with the phase of the wave signal transmitted from the sender in the CDMA system. In the sender, the signal is spread over large bandwidth by moderating the signal with a carrier signal and mixing the modulated signal with a pseudo-noise (PN) sequence. The PN sequence is represented by binary codes each having a chip duration Tc and each appearing at a chip rate Rc equal to 1/Tc Hz. The PN sequence codes partially form a group repeatedly appearing at every sequence period T. The ratio of the sequence period T to the chip duration Tc is called a "spreading ratio" or a "processing gain". The spread signal is then transmitted from the sender to the receiver.
The conventional matched filter comprises a correlator including a charge coupled device (CCD) and a surface acoustic wave (SAW) element used for calculating a correlation value between the received wave signal and a predetermined reference code sequence to obtain a desired wave signal. The CCD or SAW can be regarded as a delay line utilized for an analog signal.
The conventional matched filter of this type for calculating the correlation is disclosed by Japanese Non-examined Patent Publication No. 5-136779. The conventional matched filter thus disclosed comprises first, second, third and fourth hold units 11, 21, 31 and 41, first, second, third and fourth multipliers 13, 23, 33 and 43 and an adder 50 as shown in FIG. 11. The reference code sequence is represented by a series of four codes each having a chip duration Tc. In this case, the sequence period T is four times as longer as the chip duration Tc. Therefore, the spreading ratio of the matched filter is four chips.
Each of the first, second, third and fourth hold units 11, 21, 31 and 41 has an input terminal and an output terminal and is designed to hold an input signal inputted through the input terminal for a predetermined delay duration and to output the signal through the output terminal after the delay duration. The delay duration is equal to or less than a quarter of one chip duration Tc/4 in the conventional matched filter. The second, third and fourth hold units 21, 31 and 41 are electrically connected to the first, second and third hold units 11, 21 and 31 through the input terminals of the second, third and fourth hold units 21, 31 and 41, respectively. Accordingly, the first, second, third and fourth hold units 11, 21, 31 and 41 are integrally formed into a shift register used for successively holding the input signal and serve as the delay lines. The first, second, third and fourth hold units 11, 21, 31 and 41 may be constructed from flip-flop circuits.
Each of the first, second, third and fourth multipliers 13, 23, 33 and 43 has first and second input terminals and an output terminal and is designed to multiply data inputted through the second input terminal by a coefficient inputted through the first input terminal to output the product through the output terminal. The coefficients inputted to the first, second, third and fourth multipliers 13, 23, 33 and 43 are represented by the reference characters "A1", "A2", "A3" and "A4", respectively, in FIG. 11. The coefficients A1, A2, A3 and A4 are invariable and each indicates data at each distortion of the phase of the desired signal corresponding to each chip duration Tc in the sequence period T.
In the CDMA system, the reference code sequence comprises predetermined codes serially aligned, each having one chip duration Tc and being constructed from +1 or -1. Therefore, the multipliers in this kind of matched filter may be supplied with the coefficient +1 or -1.
The adder 50 has first, second, third and fourth input terminals and an output terminal. The adder 50 is designed to add inputs through the first, second, third and fourth input terminals to output the sum through the output terminal. The adder 50 is electrically connected to the first, second, third and fourth multipliers 13, 23, 33 and 43 through the first, second, third and fourth input terminals, respectively. The inputs through the first, second, third and fourth input terminals of the adder 50 are sequentially added to the preserved data in the adder 50. This means that the adder 50 should carry out adding operations four times in one chip duration Tc in order to output a correlation value represented by the reference character "Y(t)" in FIG. 11 at the chip rate Rc.
The manner of over-sampling the input signal at a chip rate Rc of two sampling times to one chip duration Tc by the use of the conventional matched filter will now be explained. This kind of matched filter comprises another pair of fifth, sixth, seventh and eighth hold units (not shown) in addition to the first, second, third and fourth hold units 11, 21, 31 and 41 as shown in FIG. 11. The fifth hold unit has an input terminal through which the input signal X(t) is inputted, and is designed to be held for a half of the described above delay duration. The fifth hold unit also has an output terminal through which the input signal X(t) appears after the half delay duration. The sixth, seventh and eighth hold units are similar to the fifth hold unit.
The matched filter thus constructed can over-sample the input signal X(t), i.e., the number of sampled signal, obtained by these hold units are two times as large as those obtained in the matched filter shown in FIG. 11. In the case where the matched filter is adapted to over-sampling the input signal at the chip rate Rc of four sampling times to one chip duration Tc, the matched filter is required to prepare the hold units four times as much as those of the matched filter shown in FIG. 11.
However, a drawback encountered in the conventional matched filter of the above-described nature is that all of the constructed circuits in the conventional matched filter simultaneously operate, thereby consuming a large amount of power. Furthermore, a long distance is needed for electrically wiring between the multipliers and the adder, which means that a large area on a chip element of the conventional matched filter is used by the wires. Moreover, the adder of the conventional matched filter should sum up all of the products obtained by the multipliers in one chip duration Tc, which means that the adder must operate promptly. This means that the conventional matched filter also tends to consume a large amount of power. The conventional matched filter must therefore simultaneously operate together with all of the constructed circuits, since it is impossible to carry out the operation by only using part of the constructed circuits.
A drawback encountered in another conventional matched filter adaptable to over-sampling is that the conventional matched filter lacks flexibility in its design because of the fact that the matched filter needs a plurality of additional hold units corresponding to a ratio of over-sampling times to one chip duration Tc. Moreover, the additional hold units are available for only over-sampling, but not available for the matched filter which stops over-sampling. This results in that the matched filter can decrease its utilization factor.